8@( qDgumstix,omap3-overo-palo43gumstix,omap3-overoti,omap3430ti,omap3 +!7OMAP35xx Gumstix Overo on Palo43chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/serial@4806a000T/ocp@68000000/serial@4806c000\/ocp@68000000/serial@49020000 d/displaycpus+cpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmu@54000000arm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-busyh +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-busy + pinmux@30 ti,omap3-padconfpinctrl-singley08+;defaultISpinmux_uart2_pins [<>@BSpinmux_i2c1_pins[Spinmux_mmc1_pins0[Spinmux_mmc2_pins0[(*,.02Spinmux_w3cbw003c_pins[lSpinmux_hsusb2_pins@[      Spinmux_twl4030_pins[ASpinmux_i2c3_pins[Spinmux_uart3_pins[npSpinmux_dss_dpi_pins[Spinmux_lte430_pins[DSpinmux_backlight_pins[FSpinmux_mcspi1_pins [Spinmux_ads7846_pins[ Sscm_conf@270sysconsimple-busyp0+ p0Spbias_regulator@2b0ti,pbias-omap3ti,pbias-omapyopbias_mmc_omap2430vpbias_mmc_omap2430w@-Sclocks+mcbsp5_mux_fck@68ti,composite-mux-clock}yhSmcbsp5_fckti,composite-clock}Smcbsp1_mux_fck@4ti,composite-mux-clock}yS mcbsp1_fckti,composite-clock} Smcbsp2_mux_fck@4ti,composite-mux-clock} yS mcbsp2_fckti,composite-clock} Smcbsp3_mux_fck@68ti,composite-mux-clock} yhSmcbsp3_fckti,composite-clock}Smcbsp4_mux_fck@68ti,composite-mux-clock} yhSmcbsp4_fckti,composite-clock}Sclockdomainspinmux@a00 ti,omap3-padconfpinctrl-singley \+pinmux_twl4030_vpins [Saes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocks+virt_16_8m_ck fixed-clockYSosc_sys_ck@d40 ti,mux-clock}y @Ssys_ck@1270ti,divider-clock}ypSsys_clkout1@d70ti,gate-clock}y pdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}Sdpll4_x2_ckfixed-factor-clock}corex2_fckfixed-factor-clock}Swkup_l4_ickfixed-factor-clock}SNcorex2_d3_fckfixed-factor-clock}Scorex2_d5_fckfixed-factor-clock}Sclockdomainscm@48004000 ti,omap3-cmyH@@clocks+dummy_apb_pclk fixed-clockomap_32k_fck fixed-clockS@virt_12m_ck fixed-clockSvirt_13m_ck fixed-clock]@Svirt_19200000_ck fixed-clock$Svirt_26000000_ck fixed-clockSvirt_38_4m_ck fixed-clockISdpll4_ck@d00ti,omap3-dpll-per-clock}y D 0Sdpll4_m2_ck@d48ti,divider-clock}?y HS dpll4_m2x2_mul_ckfixed-factor-clock} S!dpll4_m2x2_ck@d00ti,gate-clock}!y %S"omap_96m_alwon_fckfixed-factor-clock}"S)dpll3_ck@d00ti,omap3-dpll-core-clock}y @ 0Sdpll3_m3_ck@1140ti,divider-clock}y@S#dpll3_m3x2_mul_ckfixed-factor-clock}#S$dpll3_m3x2_ck@d00ti,gate-clock}$ y %S%emu_core_alwon_ckfixed-factor-clock}%Sbsys_altclk fixed-clockS.mcbsp_clks fixed-clockSdpll3_m2_ck@d40ti,divider-clock}y @Score_ckfixed-factor-clock}S&dpll1_fck@940ti,divider-clock}&y @S'dpll1_ck@904ti,omap3-dpll-clock}'y  $ @ 4Sdpll1_x2_ckfixed-factor-clock}S(dpll1_x2m2_ck@944ti,divider-clock}(y DS<cm_96m_fckfixed-factor-clock})S*omap_96m_fck@d40 ti,mux-clock}*y @SEdpll4_m3_ck@e40ti,divider-clock} y@S+dpll4_m3x2_mul_ckfixed-factor-clock}+S,dpll4_m3x2_ck@d00ti,gate-clock},y %S-omap_54m_fck@d40 ti,mux-clock}-.y @S8cm_96m_d2_fckfixed-factor-clock}*S/omap_48m_fck@d40 ti,mux-clock}/.y @S0omap_12m_fckfixed-factor-clock}0SGdpll4_m4_ck@e40ti,divider-clock} y@S1dpll4_m4x2_mul_ckti,fixed-factor-clock}1;IVS2dpll4_m4x2_ck@d00ti,gate-clock}2y %VSdpll4_m5_ck@f40ti,divider-clock}?y@S3dpll4_m5x2_mul_ckti,fixed-factor-clock}3;IVS4dpll4_m5x2_ck@d00ti,gate-clock}4y %VSjdpll4_m6_ck@1140ti,divider-clock}?y@S5dpll4_m6x2_mul_ckfixed-factor-clock}5S6dpll4_m6x2_ck@d00ti,gate-clock}6y %S7emu_per_alwon_ckfixed-factor-clock}7Scclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock}&y pS9clkout2_src_mux_ck@d70ti,composite-mux-clock}&*8y pS:clkout2_src_ckti,composite-clock}9:S;sys_clkout2@d70ti,divider-clock};@y pimpu_ckfixed-factor-clock}<S=arm_fck@924ti,divider-clock}=y $emu_mpu_alwon_ckfixed-factor-clock}=Sdl3_ick@a40ti,divider-clock}&y @S>l4_ick@a40ti,divider-clock}>y @S?rm_ick@c40ti,divider-clock}?y @gpt10_gate_fck@a00ti,composite-gate-clock} y SAgpt10_mux_fck@a40ti,composite-mux-clock}@y @SBgpt10_fckti,composite-clock}ABgpt11_gate_fck@a00ti,composite-gate-clock} y SCgpt11_mux_fck@a40ti,composite-mux-clock}@y @SDgpt11_fckti,composite-clock}CDcore_96m_fckfixed-factor-clock}ESmmchs2_fck@a00ti,wait-gate-clock}y Smmchs1_fck@a00ti,wait-gate-clock}y Si2c3_fck@a00ti,wait-gate-clock}y Si2c2_fck@a00ti,wait-gate-clock}y Si2c1_fck@a00ti,wait-gate-clock}y Smcbsp5_gate_fck@a00ti,composite-gate-clock} y Smcbsp1_gate_fck@a00ti,composite-gate-clock} y S core_48m_fckfixed-factor-clock}0SFmcspi4_fck@a00ti,wait-gate-clock}Fy Smcspi3_fck@a00ti,wait-gate-clock}Fy Smcspi2_fck@a00ti,wait-gate-clock}Fy Smcspi1_fck@a00ti,wait-gate-clock}Fy Suart2_fck@a00ti,wait-gate-clock}Fy Suart1_fck@a00ti,wait-gate-clock}Fy  Score_12m_fckfixed-factor-clock}GSHhdq_fck@a00ti,wait-gate-clock}Hy Score_l3_ickfixed-factor-clock}>SIsdrc_ick@a10ti,wait-gate-clock}Iy Sgpmc_fckfixed-factor-clock}Icore_l4_ickfixed-factor-clock}?SJmmchs2_ick@a10ti,omap3-interface-clock}Jy Smmchs1_ick@a10ti,omap3-interface-clock}Jy Shdq_ick@a10ti,omap3-interface-clock}Jy Smcspi4_ick@a10ti,omap3-interface-clock}Jy Smcspi3_ick@a10ti,omap3-interface-clock}Jy Smcspi2_ick@a10ti,omap3-interface-clock}Jy Smcspi1_ick@a10ti,omap3-interface-clock}Jy Si2c3_ick@a10ti,omap3-interface-clock}Jy Si2c2_ick@a10ti,omap3-interface-clock}Jy Si2c1_ick@a10ti,omap3-interface-clock}Jy Suart2_ick@a10ti,omap3-interface-clock}Jy Suart1_ick@a10ti,omap3-interface-clock}Jy  Sgpt11_ick@a10ti,omap3-interface-clock}Jy  Sgpt10_ick@a10ti,omap3-interface-clock}Jy  Smcbsp5_ick@a10ti,omap3-interface-clock}Jy  Smcbsp1_ick@a10ti,omap3-interface-clock}Jy  Somapctrl_ick@a10ti,omap3-interface-clock}Jy Sdss_tv_fck@e00ti,gate-clock}8ySdss_96m_fck@e00ti,gate-clock}EySdss2_alwon_fck@e00ti,gate-clock}ySdummy_ck fixed-clockgpt1_gate_fck@c00ti,composite-gate-clock}y SKgpt1_mux_fck@c40ti,composite-mux-clock}@y @SLgpt1_fckti,composite-clock}KLaes2_ick@a10ti,omap3-interface-clock}Jy Swkup_32k_fckfixed-factor-clock}@SMgpio1_dbck@c00ti,gate-clock}My Ssha12_ick@a10ti,omap3-interface-clock}Jy Swdt2_fck@c00ti,wait-gate-clock}My Swdt2_ick@c10ti,omap3-interface-clock}Ny Swdt1_ick@c10ti,omap3-interface-clock}Ny Sgpio1_ick@c10ti,omap3-interface-clock}Ny Somap_32ksync_ick@c10ti,omap3-interface-clock}Ny Sgpt12_ick@c10ti,omap3-interface-clock}Ny Sgpt1_ick@c10ti,omap3-interface-clock}Ny Sper_96m_fckfixed-factor-clock})S per_48m_fckfixed-factor-clock}0SOuart3_fck@1000ti,wait-gate-clock}Oy Sgpt2_gate_fck@1000ti,composite-gate-clock}ySPgpt2_mux_fck@1040ti,composite-mux-clock}@y@SQgpt2_fckti,composite-clock}PQgpt3_gate_fck@1000ti,composite-gate-clock}ySRgpt3_mux_fck@1040ti,composite-mux-clock}@y@SSgpt3_fckti,composite-clock}RSgpt4_gate_fck@1000ti,composite-gate-clock}ySTgpt4_mux_fck@1040ti,composite-mux-clock}@y@SUgpt4_fckti,composite-clock}TUgpt5_gate_fck@1000ti,composite-gate-clock}ySVgpt5_mux_fck@1040ti,composite-mux-clock}@y@SWgpt5_fckti,composite-clock}VWgpt6_gate_fck@1000ti,composite-gate-clock}ySXgpt6_mux_fck@1040ti,composite-mux-clock}@y@SYgpt6_fckti,composite-clock}XYgpt7_gate_fck@1000ti,composite-gate-clock}ySZgpt7_mux_fck@1040ti,composite-mux-clock}@y@S[gpt7_fckti,composite-clock}Z[gpt8_gate_fck@1000ti,composite-gate-clock} yS\gpt8_mux_fck@1040ti,composite-mux-clock}@y@S]gpt8_fckti,composite-clock}\]gpt9_gate_fck@1000ti,composite-gate-clock} yS^gpt9_mux_fck@1040ti,composite-mux-clock}@y@S_gpt9_fckti,composite-clock}^_per_32k_alwon_fckfixed-factor-clock}@S`gpio6_dbck@1000ti,gate-clock}`ySgpio5_dbck@1000ti,gate-clock}`ySgpio4_dbck@1000ti,gate-clock}`ySgpio3_dbck@1000ti,gate-clock}`ySgpio2_dbck@1000ti,gate-clock}`y Swdt3_fck@1000ti,wait-gate-clock}`y Sper_l4_ickfixed-factor-clock}?Sagpio6_ick@1010ti,omap3-interface-clock}aySgpio5_ick@1010ti,omap3-interface-clock}aySgpio4_ick@1010ti,omap3-interface-clock}aySgpio3_ick@1010ti,omap3-interface-clock}aySgpio2_ick@1010ti,omap3-interface-clock}ay Swdt3_ick@1010ti,omap3-interface-clock}ay Suart3_ick@1010ti,omap3-interface-clock}ay Suart4_ick@1010ti,omap3-interface-clock}aySgpt9_ick@1010ti,omap3-interface-clock}ay Sgpt8_ick@1010ti,omap3-interface-clock}ay Sgpt7_ick@1010ti,omap3-interface-clock}aySgpt6_ick@1010ti,omap3-interface-clock}aySgpt5_ick@1010ti,omap3-interface-clock}aySgpt4_ick@1010ti,omap3-interface-clock}aySgpt3_ick@1010ti,omap3-interface-clock}aySgpt2_ick@1010ti,omap3-interface-clock}aySmcbsp2_ick@1010ti,omap3-interface-clock}aySmcbsp3_ick@1010ti,omap3-interface-clock}aySmcbsp4_ick@1010ti,omap3-interface-clock}aySmcbsp2_gate_fck@1000ti,composite-gate-clock}yS mcbsp3_gate_fck@1000ti,composite-gate-clock}ySmcbsp4_gate_fck@1000ti,composite-gate-clock}ySemu_src_mux_ck@1140 ti,mux-clock}bcdy@Seemu_src_ckti,clkdm-gate-clock}eSfpclk_fck@1140ti,divider-clock}fy@pclkx2_fck@1140ti,divider-clock}fy@atclk_fck@1140ti,divider-clock}fy@traceclk_src_fck@1140 ti,mux-clock}bcdy@Sgtraceclk_fck@1140ti,divider-clock}g y@secure_32k_fck fixed-clockShgpt12_fckfixed-factor-clock}hwdt1_fckfixed-factor-clock}hsecurity_l4_ick2fixed-factor-clock}?Siaes1_ick@a14ti,omap3-interface-clock}iy rng_ick@a14ti,omap3-interface-clock}iy sha11_ick@a14ti,omap3-interface-clock}iy des1_ick@a14ti,omap3-interface-clock}iy cam_mclk@f00ti,gate-clock}jyVcam_ick@f10!ti,omap3-no-wait-interface-clock}?yScsi2_96m_fck@f00ti,gate-clock}ySsecurity_l3_ickfixed-factor-clock}>Skpka_ick@a14ti,omap3-interface-clock}ky icr_ick@a10ti,omap3-interface-clock}Jy des2_ick@a10ti,omap3-interface-clock}Jy mspro_ick@a10ti,omap3-interface-clock}Jy mailboxes_ick@a10ti,omap3-interface-clock}Jy ssi_l4_ickfixed-factor-clock}?Srsr1_fck@c00ti,wait-gate-clock}y S sr2_fck@c00ti,wait-gate-clock}y Ssr_l4_ickfixed-factor-clock}?dpll2_fck@40ti,divider-clock}&y@Sldpll2_ck@4ti,omap3-dpll-clock}ly$@4Smdpll2_m2_ck@44ti,divider-clock}myDSniva2_ck@0ti,wait-gate-clock}nySmodem_fck@a00ti,omap3-interface-clock}y Ssad2d_ick@a10ti,omap3-interface-clock}>y Smad2d_ick@a18ti,omap3-interface-clock}>y Smspro_fck@a00ti,wait-gate-clock}y ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock}y Sossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock}y @$Spssi_ssr_fck_3430es2ti,composite-clock}opSqssi_sst_fck_3430es2fixed-factor-clock}qShsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clock}Iy Sssi_ick_3430es2@a10ti,omap3-ssi-interface-clock}ry Susim_gate_fck@c00ti,composite-gate-clock}E y S}sys_d2_ckfixed-factor-clock}Stomap_96m_d2_fckfixed-factor-clock}ESuomap_96m_d4_fckfixed-factor-clock}ESvomap_96m_d8_fckfixed-factor-clock}ESwomap_96m_d10_fckfixed-factor-clock}E Sxdpll5_m2_d4_ckfixed-factor-clock}sSydpll5_m2_d8_ckfixed-factor-clock}sSzdpll5_m2_d16_ckfixed-factor-clock}sS{dpll5_m2_d20_ckfixed-factor-clock}sS|usim_mux_fck@c40ti,composite-mux-clock(}tuvwxyz{|y @S~usim_fckti,composite-clock}}~usim_ick@c10ti,omap3-interface-clock}Ny  Sdpll5_ck@d04ti,omap3-dpll-clock}y  $ L 4Sdpll5_m2_ck@d50ti,divider-clock}y PSssgx_gate_fck@b00ti,composite-gate-clock}&y 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+,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [+mcspi3 tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0+mcspi4FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-hsmmcyH Smmc1=>txrx+;defaultI8Dmmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx;defaultI8ND[hmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400vti,omap2-iommuyH mmu_ispSmmu@5d000000vti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;< commontxrxmcbsp1 txrx}fck disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>?commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx}fckickokayS mcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZcommontxrxsidetonemcbsp3mcbsp3_sidetonetxrx}fckick disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67 commontxrxmcbsp4txrx}fck disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR commontxrxmcbsp5txrx}fck disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxtimer@48318000ti,omap3430-timeryH1%timer1timer@49032000ti,omap3430-timeryI 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hsusb2_power_regregulator-fixed vhsusb2_vbusLK@LK@   p Shsusb2_phyusb-nop-xceiv  Sregulator-w3cbw003c-npoweronregulator-fixedvregulator-w3cbw003c-npoweron2Z2Z  Sregulator-w3cbw003c-wifi-nreset;defaultIregulator-fixed vregulator-w3cbw003c-wifi-nreset2Z2Z  'Slis33-3v3-regregulator-fixedvlis33-3v3-reg2Z2ZSlis33-1v8-regregulator-fixedvlis33-1v8-regw@w@Sdisplaysamsung,lte430wq-f0cpanel-dpi}lcd43;defaultI portendpointSpanel-timinga     )     ' 4 A Kads7846-regregulator-fixed vads7846-reg2Z2ZSbacklightgpio-backlight;defaultI  [leds gpio-leds;defaultIheartbeat}overo:red:gpio21  lheartbeatgpio22}overo:blue:gpio22 gpio_keys gpio-keys;defaultI+button0}button0 f button1}button1 f  compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointsinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0phandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csvcc-supplyspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxwakeup-sourceti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorspwmsmax-brightnesslinux,default-triggerti,modelti,mcbspstartup-delay-usenable-active-highreset-gpiosenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-onlinux,code